On-Chip Interconnection IP Gains Attention

By John Blyler, Editorial Director

Connecting a multitude of internal and third-party IP requires ever-advancing on-chip bus technology from big players such as ARM, OCI-IP and Intel as well as startups such as Arteris and Sonics.

The growth of third-party semiconductor core and subsystem IP has been a prerequisite for the timely development of today’s extremely complex system-on-chip (SoC) devices. But as much as IP helps, it also creates another problem: How can designers connect all these IP blocks together without sacrificing the SoC’s timing, power and performance constraints?


These interconnect challenges are the reason why on-chip communication IP continues to be a hot topic. Within the last several months, the leading mobile processor company – ARM – has announced significant enhancements to its AMBA bus technology. In that same timeframe, the leading processor IDM – Intel – drew attention to its relatively new bus structure known as the Intel On-Chip System Fabric (IOSF).

Other proprietary on-chip bus structures includes MIPS’ SoC-it and IBM’s CoreConnect, to mention a few. These buses have bridging capabilities to ARM’s AMBA bus or the Open Core Protocol (OCP) standard for IP cores (OCP-IP) socket technology. (See, “Coherent Messages from ARM and OCP?“)

Even FPGA vendors are becoming part of the on-chip communication IP equation. A significant change in the recent AMBA specification was driven by the need to accommodate FPGAs within SoC devices. The update reflected the results of several years of work between FPGA giant Xilinx and ARM. Recent update of the AMBA spec to version 4.0 now includes AXI-Streaming and Lite elements. These two additions allow ARM processors to interface directly with FPGAs (see, “FPGAs Move to IP through Processor Interface”).

Two major EDA companies focused entirely on the on-chip interconnect IP market are Arteris and Sonics. Each approaches the core-to-core communication problem in a different way.

Arteris replaces traditional on-chip, fixed-bus architectures with a packet-based, network on a chip (NOC) technology. Instead of point-to-point dedicated wire connections, the company’s NOC approach reuses existing wires. Data is sent as scheduled, layered packets across the same wires.

Sonics also uses NoC technology, but emphasizes socket-based instead of packet-based design. This emphasis highlights its use of standard networking techniques to facilitate on-chip communication. Single words replace packets. Further, Sonics does not use the globally asynchronous, locally synchronous (GALS) approach favored by Arteris.

Sonics recently celebrated its 15-year anniversary as an on-chip communication IP provider. Among the company’s milestones are the shipment of over one billion chips by customers and securing, “the largest array of on-chip communications IP of any network-on-chip (NoC) provider.”

Representatives from both Arteris and Sonics were recently interviewed by the Low-Power Engineering community. Charles Janac, CEO of Arteris and Jack Browne, senior VP of sales and marketing at Sonics, were asked by Ed Sperling to list the big issues that must be addressed in billion-gate designs. Janic said that achieving required processing power was the first need. But the second requirement was integration of IP cores. “How do you bring these cities of silicon together, which is where the communication system for the SoC becomes critical?”

Brown agreed, noting that scaling to four or eight cores requires a huge amount of parallelism and on-chip memory. “The issue we see is how you get that right, and today the solution is a lot of subsystem design.”

What lies ahead for on-chip interconnection technology? According to the International Technology Roadmap for Semiconductors (ITRS), interconnect innovation with new technologies is vital to satisfy performance and power requirements in long term support of ultra-high data rates (greater than 100 Gbps/pin). Promising future technologies include optical, RF/wireless and even carbon nano-tubes (CNTs).



John Blyler can be reached at: