More Analog Needed For Multicore SoCs

By Mike Demler, Contributing Editor

Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD Fellow Stephen Kosonocky.

In his presentation at the recent Hot Chips Conference, Kosonocky shared the experiences of the AMD Llano accelerated processing unit (APU) design team and how they addressed these challenges. By integrating a quad-core CPU architecture with a GPU in Llano, AMD was able to eliminate the power that would have been consumed by chip-to-chip I/O, and increase the bandwidth between the CPU and memory by 3X. To achieve this integration, the team implemented a complex power-management scheme that required power gating (PG) and dynamic voltage/frequency scaling (DVFS) throughout the chip, and the combination of hardware policies with operating system (OS) software interaction.

While advances in circuit design and process scaling have enabled higher levels of integration in multicore SoCs, Kosonocky showed that another limiting factor must now be considered—device packaging. The Llano APU requires six separate power supplies, including two high-current supplies. Designers can’t just add more supplies, he said, because multi-layer packaging is typically limited to only four power planes of thick high-current metal.

Aside from the cost impediment of adding more layers, package and chip designers simply run out of space. Each power layer requires its own decoupling capacitors to suppress supply noise. These chip capacitors are mounted on the package during manufacturing, and they consume available space with surrounding keep-out areas. Also, whenever another VDD is added the impact is multiplied by the increased share of package resources that must be dedicated to the VSS return path.

With packaging constraints now limiting power delivery to the number of cores that can be supported in an SoC, designers are looking to circumvent the problem by bringing external voltage regulators on-chip. Voltage regulators fall into two classes—switching circuits that use capacitors or inductors to boost and scale voltages, and linear regulators. Switching converters are generally preferred for their higher efficiency, but they require large amounts of capacitive or inductive energy storage. New solutions for power management will require more sophisticated analog circuit designs, possibly combined with additional process steps to build higher capacity passive components that are compatible with nanometer scale CMOS.

Intel, meanwhile, is investigating the use of inductive “buck converters” for on-chip voltage regulation, according to Donald Gardner, principal engineer at Intel Labs. Inductors are commonly integrated into RF ICs for wireless applications, but the current carrying capacity and inductive density of such structures is inadequate for power circuits. By adding magnetic materials to a standard CMOS process, engineers can increase the inductance of copper interconnect that is typically used in power busses. On-chip integration of a switching voltage regulator enables the use of circuit techniques to increase frequencies by more than 100 times over off-chip devices, which reduces the total inductance required by a factor of 1,000. This makes a single-chip solution feasible, and also offers the benefit of providing much finer resolution for dynamic frequency-voltage scaling, because the output of a buck converter is a function of its duty cycle.

40

The magnetic materials that Intel is evaluating include cobalt, zirconium and tantalum (CoZrTa) and nickel-iron (NiFe). Gardner said that regardless of the material, physics limits the gain in inductance that can be achieved by coupling a single layer of magnetic material to a wire to only two times, which is insufficient. Building structures that completely wrap wires in two magnetic layers, as his team is doing, is more complex but yields inductance gain that is much higher—theoretically up to the increase in the added material’s permeability.

Striped inductors (rather than spirals) are the “Holy Grail” of voltage converters, said Gardner, because the application of a magnetic field during the deposition process inevitably creates orthogonal “hard” and “easy” axes. The hard axis has the property of saturating too quickly, but laying an elongated stripe in the easy direction takes full advantage of the increase in inductance. By wrapping a thick copper wire with two layers of CoZrTa, and sealing the sides with magnetic vias to prevent flux leakage, Intel has seen inductance increases of more than 30 times compared to air-core inductors. Intel’s research has progressed to the prototype stage, with a 48-core test chip containing 8 on-chip voltage regulators that the company has distributed to researchers for further investigation of new power management techniques.

It is unclear how much additional cost would be incurred by adding magnetic materials to a fabrication process, but capacitors are an intrinsic component of CMOS transistors and are commonly used for analog/mixed-signal circuits and on-chip power supply decoupling. Elad Alon, of the University of California’s Berkeley Wireless Research Center, has explored this alternative.

41_a

In SC switched-capacitor (SC) DC-DC converters, Alon noted that efficiency is limited by conductance density, or the amount of current (or power) delivered to a load for a given voltage. A DC-DC converter could be built as a replacement in the same area as a typical decoupling capacitor, which he estimated to occupy about 10% of a chip, so that no additional cost would be incurred if the regulators delivered at least 10 times the power density that their loads consumed. A typical processor was estimated to consume about 1 watt per square millimeter, but the payoff would be even higher in a lower power mobile device, which typically has 10 times lower power density. The Berkeley Wireless Research team implemented a 32nm CMOS SOI silicon-on-insulator (SOI) test chip to test their concepts, achieving about 80% efficiency at 86 watts per square millimeter—close to the goal of 1 watt per square millimeter for a processor SoC.

Higher capacitance per area yields higher efficiency in SC converters, and losses in the bottom plate parasitic set the maximum efficiency that can be achieved. The use of dense trench capacitors, such as in DRAMs, has been shown to offer the potential of about 90% SC regulator efficiency. Alon proposed that SC voltage regulators could be integrated into about 10% of the area of a DRAM die, and used to supply the power in a processor-memory 3D IC package. Alternatively, because the power regulator circuits can be built in older, less-expensive process technologies, a dedicated converter chip could be stacked and connected through TSVs (through-silicon vias) to distribute power over the entire area of a processor die.

 


41_b

Mike Demler has more than 30 years of experience in high-tech industries spanning semiconductors, EDA software, and mobile/wireless technology. Mike was previously a Technical Editor at EDN magazine.