Micro-Packaged Discrete Devices Enable Designers to Shrink Size and Boost Performance in Portable Applications

By transitioning to flat-leaded designs and using shorter lead lengths, semiconductor manufacturers have been able to deliver a wide variety of ultra-compact discrete semiconductor devices.

Wireless handsets and other portable consumer devices are driving the trend for smart, multimedia-enabled, feature-rich devices that integrate far greater and more varied functionality. Semiconductor suppliers are responding to this trend by continuing to miniaturize the packages of the IC components that they supply. But this needs to be done without thermalperformance and power-density penalties.

As electronic products continue to shrink in size, the semiconductor devices used within those products must also become smaller, take up less real estate, and ideally have a lower profile. Miniaturized semiconductors enable smaller, lighter, and more portable products with greater functionality at a given size. Optimizing these parameters permits more compact printed-circuit boards (PCBs) that can be packed closer together. Small-signal discrete devices, such as diodes and transistors, play a vital role in portable devices by providing higher power dissipation compared to an integrated solution at lower cost per die area. In addition, small-signal discretes offer design flexibility, reuse across multiple platforms, and the ability to rapidly implement design changes. In doing so, they reduce time to market. The availability of array- style devices offering multiple discrete functionality from a single compact package also can contribute to enhanced design flexibility.

Trends In Discrete Micro-Packaging

Since the advent of the first surface-mounted discrete transistor in the SOT23 package back in the late 1970s, many companies have been engaged in the mass production of smalloutline packages. Such packages were designed to occupy the least possible area of the PCB. The progression continued with the introduction of even smaller packages, such as the SC70 and SC75. They were followed by the development of devices that combined dual transistors and diodes in a single package, further improving the PCB space efficiency compared with traditional discrete devices.

Figure 1 shows an evolution of surface-mount packages over the last two decades. Small-signal discretes have been able to continuously shrink size while boosting their thermal performance. Key factors in this improved performance have been the transition from gull-winged to flat-leaded designs and the use of shorter lead lengths, which reduce the thermal path of the silicon die to the board.

Figure 1: Modern package options, such as the SOT-963, SOT-1123, and SOD-923, occupy only a fraction of the board space needed by the commonly used SOT-23. Yet they maintain the same thermal performance, thanks in part to a shorter and flatter lead design.

Package Size Versus Thermal Performance

Semiconductor packages are commonly evaluated on the basis of thermal performance compared to PCB space consumed. A common misconception of thermal performance is that the package size always inversely corresponds to the thermal performance. In other words, the smaller the package, the worse this performance will be. While size is critical to the equation, materials and lead length play equally vital roles in ensuring that the component can dissipate the heat generated. Table 1 compares the thermal performance of the popular SOT23 package with the SOT563 using the same device silicon.

One of the keys to the improved thermal performance demonstrated in the table is that the new generation of packages combines novel approaches to lead design. For example, modern packages include shorter lead lengths and redesigns of the die-to-lead connection. The shorter the lead length, the lower the thermal resistance will be. To greatly improve the dissipation of heat from their devices, semiconductor manufacturers have reduced the lead length while making the flat area of the lead as large as possible. They also have minimized the dependence on wire bonding through techniques like direct connection of the die to the leads. This is illustrated in Figure 2a while Figure 2b shows how the new package design reduces the device profile.

By retaining leads rather than implementing a leadless structure, these smaller packages remain fully compatible with standard pick-and-place assembly equipment and the industry’s strict visual-inspection requirements. As a result, there are no additional layers of complexity added to the production process. The increased risk of faults is thus avoided. In addition, manufacturers don’t accrue any additional penalties in terms of time or cost.

By employing the techniques described previously, it has been possible for semiconductor manufacturers to deliver a wide variety of new, ultra-compact discrete semiconductor devices. Take, for example, the latest low VCE (sat) and general- purpose transistors for low-voltage, high-speed switching applications. Now available in micro-packages ranging from the three-leaded SOT1123 (1.0 x 0.6 x 0.8 mm) to six-leaded SOT963 (1.0 x 0.8 x 0.4 mm), these devices deliver space and energy-efficient control in applications like power management in portable devices and low-voltage motor control. Package reductions also have been applied to dual-transistor arrays. The latest dual bias junction transistors (BJTs) require PCB space of just 1.0 x 1.00 mm while bias resistor transistors (BRTs) allow designers to use a single device in place of a discrete transistor and its external resistor bias network. In the case of diodes, it’s now possible to obtain Schottky and Zener devices in ultraminiature SOD923 packaging. In the latter case, the devices still provide electrostatic-discharge (ESD) protection to 16 kV (in accordance with the HBM Class 3 model).

Package reductions also have been applied to dual-transistor arrays. The latest dual bias junction transistors (BJTs) require PCB space of just 1.0 x 1.00 mm while bias resistor transistors (BRTs) allow designers to use a single device in place of a discrete transistor and its external resistor bias network. In the case of diodes, it’s now possible to obtain Schottky and Zener devices in ultraminiature SOD923 packaging. In the latter case, the devices still provide electrostatic-discharge (ESD) protection to 16 kV (in accordance with the HBM Class 3 model).

Designing With Smaller Packages

For the design engineer, significant flexibility can be derived from advances in packaging that allow smaller components to be realized without manufacturers having to sacrifice any of the ability to dissipate heat energy. Yet there are still areas that need to be carefully considered when it comes to designing with these devices. For example, utilizing component arrays that deliver the functionality of multiple discrete components from a single device can offer a means of saving board space and reducing heat dissipation. But they also can place restrictions on the placement of other components during circuit layout.

Furthermore, datasheets can prove misleading, as there are notable discrepancies in the metrics used by different suppliers to define component size. Some chip vendors specify length, width, and PCB reduction measurements based on the overall space that the package will occupy on the PCB from lead tip to lead tip. Others refer only to the dimensions of the package’s molded body and exclude the leads. Take the SC88 package, for instance. Although its package width is normally given as 2.10 mm, some manufacturers may state this dimension as 1.25 mm. Clearly, realistic dimensions that represent the actual PCB space consumed including package leads are most appropriate for accurate assessment and successful implementation.

Edwin Romero is an applications and marketing engineer at ON Semiconductor in the Standard Products Group for Portable and Consumer Products. Romero joined ON Semiconductor in 2006. He received his BSEE from Arizona State University.