Embedded Instrumentation Has Intel® Xeon® Processor 5500 Series Designs Covered

Circuit boards featuring the recently introduced Intel® Xeon® processor 5500 series (codenamed Nehalem) have unique test and validation needs. Non-intrusive test technologies based on embedded instrumentation vow to provide the required test and validation coverage. Such coverage has become increasingly critical because it has diminished in recent years from older, intrusive test technologies like incircuit test (ICT), manufacturing defect analyzers (MDAs), flying probe testers, and others. As a result, non-intrusive embedded instrumentation test technologies will be required to thoroughly test and validate new embedded applications featuring this processor series.

Diminishing Coverage

Test and validation coverage from intrusive probe-based test technologies has eroded over the last decade for a number of reasons. For instance, the physical access that test probes rely on has been rapidly disappearing. In addition, the high speeds and capacitive sensitivities of today’s leading- edge designs, such as those based on the Intel Xeon processor 5500 series, make the use of intrusive probe-based technologies unsatisfactory if not impossible.

Historically, physical test access was obtained by placing a probe on a device pin or a test pad that had been designed into the circuit board. Advancements in device packaging have severely limited the availability of device pins for test purposes. Fine-pitch pins and chip-scale packaging techniques like ball grid arrays (BGAs) deny physical access entirely, as pins are replaced by balls underneath the die. Heatsinks also can limit or block physical access.

Test pads are disappearing from circuit boards as well. These small contact points were typically placed on the board’s surface to give access to interconnect buses for test and validation purposes. But placing a test pad on a highspeed serial bus introduces capacitive anomalies on that bus, which in turn raise signal-integrity issues. An example of such a bus is Intel® QuickPath Interconnect (QPI), which is deployed on Intel Xeon processor 5500 series designs as well as PCI Express, Fibre Channel, 10-Gbps Ethernet, InfiniBand, and others. Because of these signal-integrity issues, the test or validation measurements obtained by placing a probe on a test pad become unreliable. The problem is that the capacitive anomalies introduced by the probe cannot be distinguished from the high-speed serial signals on the bus.

Delivering Coverage: Embedded Instrumentation

There are alternatives, which also can complement the older intrusive technologies. Several newer, software-driven, non-intrusive test technologies make use of the embedded instrumentation that’s being placed in contemporary devices. This embedded instrumentation is either proprietary or open-standards-based intellectual property (IP), which enables the test and validation of chips, boards, and systems. Examples of embedded instrumentation technologies include the proprietary Intel® Interconnect Built-In Self Test (IBIST), processor-controlled test (PCT), and the IEEE 1149.1 boundary- scan standard.

Figure 1: The results of an Intel® IBIST margin test are displayed
on the ASSET® ScanWorks® IBIST Results Viewer.

The Intel IBIST was designed as a built-in self-test technology. It is being embedded by Intel, Avago, and other semiconductor companies into their next-generation chips and chip sets. The embedded Intel IBIST functionality can be applied in a number of ways including non-intrusive structural tests on circuit boards. It also can be used in design- validation applications to validate the performance of high-speed serial buses. The current primary use of Intel® IBIST is circuit-board validation testing. Here, pattern generation and checking, bit-error-rate (BER), and margining tests are applied to confirm a board design’s signal integrity. Figure 1 shows the results of an IBIST margin test.

A second non-intrusive test technology, which would be appropriate for testing Intel Xeon processor 5500 series designs, is boundary scan. This IEEE standard was ratified in 1990. Its adoption by the industry accelerated rapidly in the mid-1990s as BGAs and other types of chip packages denied access to device pins. Essentially, IEEE 1149.1 boundaryscan tests are applied to a circuit board through a connector and a four-wire serial interface called the test access port (TAP). When implemented in chips, this interface is commonly referred to as the JTAG port. This term comes from the informal name of the working group that initiated the standard’s development: the Joint Test Action Group.

Since its development, the boundary-scan standard has been adopted extensively by the industry. It’s now deployed in chips as well as on circuit boards and in systems. Because of its widespread acceptance, the boundary-scan infrastructure has been appropriated by other applications and related standards. It is used to program logic and memory devices in-system, for example. In addition, it provides the basis for the IEEE 1149.6 standard for testing high-speed, AC-coupled interconnects and other standards. The boundary-scan standard also is a foundational standard for several emerging standards including the two-wire IEEE 1149.7 compact and enhanced boundary-scan standard as well as the IEEE P1687 Internal JTAG (IJTAG) standard for accessing, automating, and analyzing embedded instrumentation.

A third, non-intrusive test technology for Intel Xeon processor 5500 series circuit boards is processor-controlled test (PCT). PCT makes use of the boundary-scan infrastructure on a circuit board to access and apply the extended debug commands provided by a board’s processor. Control of the processor is temporarily given over to the PCT system so that the CPU can be used to read and write memory and input/output (I/O) registers in addressable devices. In this way, PCT exercises the functionality of the board and—as a byproduct—detects and diagnoses structural faults.

Because it’s a functional test, PCT is device- and buscentric. That is, it exercises specific devices and buses on a circuit board. It also operates at CPU speeds, which means that this “at-speed” test will detect faults that only manifest themselves while the board is running at operational speeds. In contrast, boundary scan is a static test technology. Taken together, the two technologies provide coverage for a broad spectrum of structural and electrical faults.

Applying Embedded Instrumentation To Intel Xeon processor 5500 series-based Boards

Figure 2 shows a typical and rather simple topology of an Intel Xeon processor 5500 series-based circuit board. Virtually the entirety of this board can be tested with the three non-intrusive test technologies: Intel IBIST, boundary scan, and PCT.

Figure 2: This figure shows a common Intel® Xeon® processor
5500 series-based circuit-board topology.

For the QPI and PCIe links, Intel IBIST can be used to validate the shape and size of an eye diagram via margining tests. A BER test can be applied to identify any performance issues on these high-speed serial buses. Moreover, a four-corner or fast-cross test can be employed with IBIST technology to verify link speeds, determine the size of the eye on a link, and detect some structural faults.

Figure 3: Non-intrusive test and validation coverage are
provided for a Green City reference design.

PCT can exercise the kernel of the board’s devices and buses with an at-speed functional test. Because it is a lowlevel (pre-boot) functional test, PCT can run without the BIOS or operating system (OS) loaded. In addition, PCT has excellent diagnostics. And it runs much faster than traditional functional tests. When deployed as a complementary technology to in-circuit test (ICT), PCT can reduce the number of test points required in the ICT test fixture. In doing so, it dramatically reduces fixture costs.

The third non-intrusive test technology—boundary scan—can be used to test the board’s electrical continuity where it’s impossible to place test pads, such as on the QPI links. Boundary scan also can be used to reduce the number of test points that are typically needed by ICT test fixtures— again reducing fixture costs. In addition, boundary scan can be used for the lifecycle of the product beginning with prototype testing, continuing through manufacturing, and also utilized in repair and return applications. Figure 3 illustrates the extensive coverage that these three non-intrusive test and validation technologies can deliver on one of the Intel Xeon processor 5500 series customer reference designs—the greencity board.

The Test Challenge

The Intel Xeon processor 5500 series (codenamed Nehalem) represents a two-edged sword. On the one hand, their breakthrough combination of processing power and low power consumption ensures their deployment in a wide range of embedded applications beyond Intel’s traditional scope in desktops, laptops, and other computers. Certainly, the Xeon® 5500 processor series will find its place in routers, storage systems, wireless base stations, security appliances, weapons systems, embedded computers, and many other types of embedded applications.

On the other hand, these designs present a number of test and validation challenges that by and large cannot be overcome solely by older, intrusive test technologies. Fortunately, newer non-intrusive, software-driven test technologies like Intel IBIST, processor-controlled test, and boundary-scan test offer alternatives while complementing the older technologies. As a result, the goal of high levels of test and validation coverage can be achieved.

Tim Caffee is vice president of design validation. His business unit is responsible for bringing new tools to market that will validate the design of nextgeneration products. Tim was a founder of ASSET and has spent 15 years working with boundaryscan tools. He obtained BS degrees in mathematics and computer science at Virginia’s Old Dominion University.