Next-Generation System Interfaces Raise Data Rates for USB and PCIe

There’s more changing than mere speed.

By Dave Bursky, Contributing Editor

As systems handle larger amounts of data, there also is a need to transfer that data in short amounts of time. Because of this demand, interfaces like the popular Universal Serial Bus (USB) and PCI Express (PCIe) must operate at higher speeds. Efforts to define the next-generation USB and PCIe interfaces, which operate at data rates of 300 MBytes/s for USB 3.0 and up to 8 Gtransfers/s for PCIe 3.0, are underway by both the USB and PCI Special Interest Groups. These data rates can cut current data-transfer times by at least fivefold for USB. Table 1 makes this point by comparing the three generations of USB transfer speeds for different-sized file transfers. Similarly, PCIe 3.0 doubles the transfer rate of PCIe 2.0 (see Table 2).

Table 1: Comparison of data transfer rates for three generations of USB interfaces

Table 2 – Data transfer rates for the three PCIe generations

 

Also referred to as SuperSpeed USB, the next-generation USB interface includes a “Synch and Go” capability. With extensive power management embedded in the media-access-control (MAC) and physical-interface (PHY) portions of the controller, the Synch and Go capability was designed to work in mobile platforms. In fact, this interface promises to provide plenty of headroom for all Flash-memory-based peripherals, such as digital cameras, camcorders, memory drives, smart phones, and many industrial systems that are embracing Flash storage.

What’s different in USB 3.0? Aside from the higher datatransfer speed, designers added a dual-simplex datapath. They also revised the USB protocol without requiring any auxiliary signals (no reference clock, reset signal, etc.). Figure 1 shows a side-by-side comparison of the two interface-signal sets and the two additional twisted pairs for the dual-simplex datapath, which is incorporated in the USB 3.0 cable. Yet the cable interface remains backward-compatible with USB 2.0. The basic 2.0 interface is still intact.

For peripherals and other operations, only one bus connection is allowed to be active at any point in time. Inside the hubs, however, USB 2.0 and 3.0 bus trees will operate independently of each other. For compound peripherals with integrated hubs, the multi-bus operation is only allowed for the hub portion of the peripheral.

The Superspeed interface can support up to a 3-meter cable and deliver up to 300 MBytes/s for storage-class devices. The connectors that are used for the interface can fit the current USB 2.0 Type-A and Micro-B form factors. In addition, the systems retain the USB hot-plug capability. As a result, the use of the SuperSpeed interface is almost transparent to the user.

It should be noted that the Standard-B connector is visually different from the USB 2.0 Standard-B connector. Yet USB 2.0 cables can plug into the USB 3.0 Standard-B connector. The Micro- B connector for USB 3.0 is an extended version of the 2.0 Micro-B connector, which adds a second connector section for the additional signals required by USB 3.0. USB 2.0 Micro-B connectors can plug into the 3.0 version of the connector.

When comparing the SuperSpeed USB interface to other high-speed interfaces, such as SATA or PCI Express, there are a few differences. Even though SuperSpeed USB doesn’t use a common clock architecture, for example, it does require the use of spread-spectrum signaling on both sides of the interface. Additionally, equalization is required on the receive side of the interface. The link layer was designed to be robust. Redundancy and advanced encoding techniques as well as error management are all incorporated in the link layer.

In addition, both the upstream and downstream ports can initiate lower-power states on the link. Doing so will provide control of the four power states that are incorporated in the link layer, thereby minimizing power consumption during idle periods. The four states are defined as U0 (active data transfers), U1 (link idle, but internal PLL remains on), U2 (link idle, but PLL may be off), and U3 (suspend).

When the host initiates a transfer to a device that’s connected through a hub—and the link on the device side of the hub is in one of the low-power modes—the hub will send a deferred command back to the host. The hub will then forward the original packet header to the device, thereby waking it up. This approach allows the host to initiate transfers with other devices while the initial device wakes up and notifies the host that it’s ready to complete the transfer. As a result, the host never has to wait for a device. This aspect maximizes the data throughput.

Figure 1: Side-by-side comparison of the two interface signal sets and the two additional twisted pairs incorporated in the USB 3.0 cable.

Moving data over the link includes three steps: link training, packet formation, and error handling. Data packets contain both a header and the data payload. In addition, transaction packets manage the flow of data. The USB host initiates all data transfers. Devices can either respond immediately or defer their response. Deferred requests are restarted asynchronously with the device notifying the host. The host then responds with a new transfer request.

For high-speed transfers within a system, PCI Express has become the dominant interface in PC and industrial systems. As fast as PCIe 2.0 is, however, it’s not fast enough for high-performance graphics and other data-intensive applications. To meet speed demands, designers are now close to finalizing the specifications for PCIe 3.0. This version will offer data transfers of up to 8 Gtransfers/s.

Basically, PCIe 3.0 will be backwards compatible with PCIe 1.x and 2.0 (no changes to the connectors, card form factors, or material). It will preserve existing data-clocked and common- clock architectures. The PCIe 3.0 channels also will have a similar “reach” on the system boards: for mobile applications, up to 8 inches with one connector; in desktop systems, up to 14 inches with one connector; and in servers, up to 20 inches with two connectors.

The PCIe 3.0 PHY interface for PCI Express (PIPE) is an extension of the PCIe 2.0 PIPE. It adds 32-bit data widths (up to 32 parallel serial channels), new clocking options, and a control signal for the MAC to tell the PHY to ignore 8 bits. The MAC also uses the control signal to handle 128/130-bit domain rate differences. The PIPE layer handles the low-level PCIe protocol and signaling, which includes functions like data serialization and deserialization, 8b/10b encoding, and 128b/130b encoding as well as the analog buffers, elastic buffers, and receiver detection.

To add more flexibility to the interface, the forthcoming specification will include an atomic read-modify-write transaction capability. This capability will extend interprocessor synchronization mechanisms to the I/O. Other features added to the 3.0 interface include an ID-based transaction ordering capability, which can help to reduce transaction latencies in a system. In addition, a multicast transaction capability permits performance scaling of existing applications. It also could create new usage modes for PCIe. By including more dynamic power/thermal control capabilities, the specification plans to better handle highpower boards, such as graphics processors, that are plugged into the interface (up to 300 W for an add-in card).

Want more information? Go to the USB Developer website at www.usb.org. For PCI Express 3.0, visit www.pcisig.com.

Dave Bursky is a contributing editor for Chip Design and Embedded Intel Solutions magazines. He also is the technical editorial manager at Maxim Integrated Products Inc. in Sunnyvale, CA.