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Standards Efforts Move Multicore Design Forward

By Cheryl Ajluni

The increasing demand for greater performance, functionality and new, more creative products has driven leading device manufacturers to pursue an alternative to traditional single-core processor designs. Growing industry consensus points to one solution - multicore design. Defined as the placement of two or more cores on a single chip, multi-core design provides the much sought after performance increase while also keeping power under control. As a result, it has been deemed by many as one of the most important milestones in computing in recent years.

Unfortunately though, multiprocessing comes at a price. It introduces increased levels of complexity which in turn create new obstacles for the semiconductor industry - not the least of which is a lack of adequate development tools for programming and debugging multicore systems. That complexity will only increase as the number of cores per chip multiplies. Programmers therefore, have to behave differently as do compliers, languages and operating systems. New skills, techniques and tools for designing, coding and debugging will be required. Fortunately, both hardware and software vendors are developing tools and methods to address this need. But, in order for widespread proliferation of multicore design to occur, those solutions must be based on standard, as opposed to proprietary, solutions. Without standards and standards-based technologies to ensure the choice, flexibility and ease-of-use that today's manufacturers require, the industry's transition to multi-core design will be severely hampered.

Leading The Way
One organization working to address the standards issue for those working with, and/or proliferating multi-core-related products, including processors, infrastructure, devices, software, and applications is the Multicore Association. Officially created in November of 2005, its goal is to develop standard interfaces to debug and Electronic Design Automation (EDA) tools in support of multicore design.

According to Markus Levy, president of the Multicore Association, "Chips of the future will combine ever more heterogeneous cores, interconnects, hardware accelerators, and memory hierarchies. The potentials of parallel processing on such SoCs are tremendous, but so are the challenges of harnessing this processing capability in a way that supports interoperability and thus helps speed time-to-market. This situation highlights the need for industry standards, such as those being developed by the Multicore Association, to help vendors and customers create more successful multicore designs."


In particular, the Multicore Association has identified the need for three separate, but somewhat related standards, in this area. They include the Communication Application Programming Interface API (CAPI), the Transparent Inter Process Communication (TIPC) protocol which is specially designed for intra-cluster communication, and multicore debug mechanisms that support interoperability between tools.

Of the three identified areas of interest, the one garnering the lion's share of the attention these days is the CAPI embedded API. It will feature properties similar to those of other industry standards such as Message Passing Interface (MPI) and OpenMP, but with its minimal overhead and performance characteristics, it will be able to fully exploit the proximity of multiple cores integrated into a single chip (see Figure 1). As a result, this message passing and resource management API will capture the basic elements of communication and synchronization that are required for embedded distributed systems (see Figure 2). Specific target systems for CAPI will span multiple dimensions of heterogeneity, including core, interconnect, memory, operating system, software tool-chain, and programming language.

The Multicore Association's CAPI working group is currently working to define application use cases for the CAPI specification. Such usages will include automotive (engine control), networking (router), and a consumer multimedia application.

The other area that the Multicore Association is focusing on, and which ties into the work being done by the CAPI working group, is multicore debug. Most vendors these days claim that their tools intrinsically support multicore and multiprocessor systems using any combinations of embedded processor types. As an example, consider that existing solutions consist of a JTAG probe with a "tap server" on the bottom end, and different instances of monolithic debuggers - one for each different core - on the top end. While this solution may be viable for multi-core debugging, accommodating a multicore design with more than 2 cores can be rather brutal. The idea of running 16 different debugger instances to debug a 16-core system just isn't a practical option. The multicore debug working group is working to address this issue by developing a standard debug protocol/API which would allow vendors to easily debug large multicore systems.


Other Efforts Underway
The Multicore Association is not the only one working toward the creation of standards to govern multicore design. Intel Corporation and Wind River Systems are also actively working to drive the adoption of multicore design through various educational efforts and industry initiatives.

Intel is currently in the midst of transitioning its processors from single-processor engines to ones that will have multiple cores and threads. By year's end, more than 75 percent of its mainstream server, desktop and laptop PC processors are expected to ship as dual-core processors; with four-, eight- and many-cores on the horizon. Recognizing the impact of this transition on software design and the need for solutions to leverage the processing power such multicore design provides, Intel is partnering with universities on a curriculum for future milticore processors as well as on software-related research. In the latter case, that collaboration will involve the creation of a public suite of applications for multicore processors which may ultimately be used as a benchmark for multicore chips.

According to Renee James, corporate vice president and general manager of Intel's Software and Solutions Group, "To usher in a new generation of computing technology and bring creative new products to market, it's crucial to educate tomorrow's software developers to architect, develop and debug the next generation of software for modern, multi-core platforms."

A total of 45 universities worldwide will be working with Intel to prepare university students for the new paradigm of software development. As part of this higher education program, Intel will provide the universities with expertise, funding, development materials, and on-site training to help them incorporate multi-core and multi-threading concepts into their computer science curricula.

Wind River's contribution to the area of multicore design comes in the form of the Multicore Processing (MCP) initiative. It is designed to drive standardization and will provide device manufacturers with the software solutions they need to build devices which leverage the performance benefits of multi-core components.

MCP will leverage Wind River's Eclipse-based Workbench development suite which provides advanced multi-core development and debugging capabilities while supporting both heterogeneous operating systems and/or heterogeneous processor architectures. Wind River's Workbench Diagnostics debugging tool will help pinpoint time consuming, extremely hard to find multiprocessing problems like race-conditions.

Conclusion
While multicore design is clearly the way of the future, many uncertainties remain about how to best leverage its benefits. What is clear is that creating software which can make full use of multicore hardware to offer greater performance or reduce energy use will need to be a critical part of this technology transition. A move away from multicore hardware and software implementations based on proprietary solutions will also aid in this transition, as will the drive towards heterogenous embedded distributed systems.