Designing Ethernet to USB Networking Connectivity with a Franchisable Embedded Platform (FEP)By Sam Sanyal, MosChip Semiconductor Corporation
The emergence of system-on-chip (SoC) technology has brought a plethora of embedded opportunities to address some of the issues of today’s multiple vertical segments. At the same time, it has introduced a spectrum of design challenges. With the advancement in silicon geometry (down to 45nm), today we are able to implement multiple functional blocks (from multi-core to multi-IO standards) on a single die with programmable options, all the while reducing device costs and adding security and stability to SoCs. Performance and data integrity are directly related to multiple latencies and design security issues, and where multiple IO standards are employed, this scenario becomes even more significant. Other than test, simulation, and verification, the challenge is to narrow the disconnect between the hardware and software integration.
To that extent, Franchisable Embedded Platform (FEP) can play a key role in enabling quick repurposing of existing designs. FEP can help designers meet the latest connectivity requirements and turn around new designs within a limited marketing window. FEP can also aid in meeting price targets and maintaining systems performance and compatibility with industry standards. The combination of USB, Ethernet, and the use of FEP is worth the consideration to meeting the integration challenges.
Franchisable Embedded Platform (FEP)
A Franchisable Embedded Platform (FEP) can play a key role in enabling quick repurposing of existing designs, thus maintaining maximum system performance while minimizing design requirements and costs. Essentially, the concept of FEP is to create a base design from which new designs can be quickly developed. Typically, if the base design is done right, subsequent modifications can be swiftly created while minimizing new design issues and costs and performance problems.
It’s important to look at FEP as an approach that enables designers to better take advantage of advancements brought by SoC technology. FEP alleviates many key design challenges within a design cycle and minimizes design times given its concept of quickly re-purposing an existing design. FEP enables embedded designers to create a base platform that addresses multiple design requirements of a market segment and thus, create multiple systems that allow for incremental modifications without re-creating the entire wheel. You can think of FEP like the fashion industry might think of a shirt. A fashion designer creates a base shirt design that might include a cotton fabric of such weight and length, etc. Then, the fashion designer can modify this base design with varying buttons, a different collar, color, etc. to quickly bring new shirts to market. Similarly, FEP lets embedded designers re-spin the same platform into new designs to address new application needs.
Connectivity and FEP
There are priorities and tradeoffs to consider in creating a base design. For example, you might need to consider if integration or dis-integration is beneficial to the end application. To this end, you might create a base platform that allows you to be selective in integrating relevant functional blocks. If you had created a system with Ethernet to USB, and you later come to realize a new market requirement for Ethernet to PCIe, FEP makes it possible to reconfigure the existing device with EPROM with a few physical connectivity changes to quickly arrive at a new design.
Connectivity design considerations include different protocol standards and the implementation of the logical link layer, MAC layer, and physical layer, as well as how these stitch to the IOs to be used.
The best place to stitch such multiples blocks of IO standards - such as, Ethernet, USB, PCI, PCIe, ISA, GPIO, etc. - is on one single die. Such SoC connectivity can be stand-alone or put together around an embedded processor, such as ARM 9. This approach should remove most delay issues, enhance integrity, and add data crossover security. In addition, a reduction in component costs can be realized all the while minimizing design-in time since all data paths and implementations will be on-chip.
Now that we’ve created a base platform, the designer should be able to create multiple applications merely with an EPROM configuration for the specific crossover bridge such as 10/100/1000 Ethernet to USB, or PCIe to USB. And thus, one platform can be franchised across whatever connectivity options need to be addressed today or tomorrow.
One platform can be franchised across whatever connectivity options need to be addressed today or tomorrow. One application that seems most ideal for a FEP-based implementation is the combination of USB and Ethernet. Such combination can address multiple applications such as USB file server, NAS, printer server, SOHO, docking stations, display, and others. However, with USB to Ethernet, bandwidth requirement at the back do have to be higher to alleviate network bottleneck, and an Ethernet 10/100/1000 port should be incorporated as part of the solution.
With a quick replacement of one functional block for another, or replacement of a peripheral card to accomplish new specific functions, moving into a different domain-specific area can be accomplished quickly when an opportunity arises. Source code compatibility will also contribute to ensuring a fast time-to-market, since given the base design, lengthy code modification should not be required.
MosChip has developed a number of domain solutions (storage, consumer, IPC and others) with FEP using its Network Appliance Processor SoC. Interoperable functional blocks that include Ethernet, USB, PCIe, ISA, GPIO, among others, are designed and are readily available. This makes for an ecosystem that has a myriad of design options, allowing quick swap out of functional blocks to create new high performance designs in rapid time.
Opportunities to benefit from FEP exist in the low-end of convergence consumer and industrial products. It is in such markets where change happens fast and where quick incremental changes in system design can allow an existing product to quickly morph to meet new market requirements in a cost effective manner.
It goes without saying that market knowledge about all applicable verticals and their respective cost-estimation is a must. Understanding these market dynamics helps with developing the architecture and in knowing what functional blocks to use.
Shorter design time, meeting performance targets, reducing costs, catering to diverse applications, and meeting schedules – such are the business requirements of embedded design engineers. Within the confines of these requirements, from a design view, it is all about on-chip and off-chip performances, about processing and interoperability among IO standards, and about the design of a differentiated product that can be turned around within a discriminating schedule.
The extremely competitive embedded market nowadays rarely allows for long marketing windows. This is especially true in Asian markets where IO protocols and performance are often seen as key attributes in maintaining market shares. For developers in these geographic areas, a Franchisable Embedded Platform (FEP) approach is increasingly ideal. Executed appropriately, FEP will let you keep the shirt on your back by delivering high performance and costcompetitive designs that meet the latest performance and IO demands.
Sam Sanyal is the Applications and Marketing Manager at MosChip Semiconductor. He has nearly 26 years of experience in the semiconductor industry in various applications, design, FAE and Technical Marketing management positions. Sam can be reached at email@example.com.