Network Processors and CompactPCI

By ADLINK Technology

One of the more specialized processors in today’s marketplace is the network processor. This processor is intended to manipulate packet-based data at line rate speeds. Over the last few years, silicon vendors have been actively touting network processors over ASICs in WAN edge/access aggregation, wireless infrastructure and Layer 4-7 switch applications. This article will take a look at some of the PCI Industrial Computer Manufacturers Group (PICMG®) standards that are typically used with network processors and introduce the 6U CompactPCI Network Processor Board from ADLINK.

PICMG 2.0 and PICMG 2.16 Architecture

Network Processor Data Transport Interfaces

When using network processors in standards based CompactPCI platforms, one of the first challenges is how to handle the data transport interfaces that a network processor provides. Network processors typically use packet-based interfaces to connect PHY devices. Some of the common interfaces are Universal Test and Operations PHY Interface for ATM (UTOPIA), Packet Over SONET PHYsical (POS-PHY) interface, and System Packet Interface level 3 (SPI-3). To complicate matters further, some of the interfaces support multi-PHY mode allows an interface to support multiple PHY devices. As you can see, the type of interface used for the main data path on network processors is significantly different from the PCI bus used in traditional CompactPCI boards. Early adopters of network processors on CompactPCI recognized the need to provide a flexible interface that could support the packet-based data transports of the future.

cPCI-6240 Block Diagram

I/O Mezzanines

CompactPCI and VME board developers often use PMC sites as a method to provide additional I/O capability. PMCs can be added to the board to augment the I/O payload of the board. Typical PMCs include mass storage, network, and general purpose I/O. The PMC specification uses the PCI bus as the interface between the board and the PMC module. PCI was chosen as the interface because of its ubiquitous nature; almost any I/O function desired could be found with a PCI interface. The PMC interface has served the CompactPCI and VME markets well, but lacked the packet based data transport interfaces required by network processors.

In August 2001, PICMG released PICMG 2.15 PCI Telecom Mezzanine Card (PTMC) specification. This specification was intended to support 4 popular industry standard telecom bus interfaces (H.110, Utopia Level 2, POS-PHY, and RMII) as well as support for the existing 32 and 64 bit PCI bus. PICMG released an ECR to PICMG 2.15 at the end of 2002. This ECR expanded the number of configurations supported from 4 to 7 by adding Ethernet capabilities to TDM and UTOPIA configurations. The flexibility provided by PICMG 2.15 comes at a price, namely ease of use. The PICMG 2.15 subcommittee had to live within the pins available in the PMC specification. This limitation required that specific configurations and pin usages be documented and also required that the pins traditionally used for the upper 32-bit of 64-bit PCI interface be redefined to support the new I/O capabilities limiting PTMCs to 32-bit PCI interfaces. When using PTMCs it is important to verify that the PTMC and board it plugs into (carrier card) support the same configuration.

cPCI-6240: ADLINK 6U CompactPCI Network Processor Board

PICMG 2.16

The next piece in this design is the IP data transport. This transport should provide redundant Ethernet links for fault tolerance and enough bandwidth to handle the required traffic. In September 2001, PICMG approved the PICMG 2.16 Packet Switched Backplane specification. This specification defines dual10/100/1000Mbit Ethernet interconnects for CompactPCI boards. PICMG 2.16 compliant systems have been deployed in a variety of applications. The ubiquitous nature of the Ethernet interconnects and the need for IP data transports has led to high levels of adoption among system providers. The figure below shows the IP connectivity. It is interesting to note that this example removes the PCI bus from the CompactPCI system. The industry is starting to see a migration away from PCI and towards IP for connectivity in platforms that handle IP based traffic. This is an example of a possible implementation.

PICMG 2.0 and PICMG 2.16 Architecture

In architecting a CompactPCI board that converts ATM to IP one might want to add some flexibility beyond what has been discussed. In many cases, the application might require additional general purpose processing power to handle exception packets. An additional PMC site could be added to support a processor PMC. It is also likely that a user might want to access the IP traffic from the front of the board for test. Front mounted Ethernet connections might also be used for boards that need to route IP traffic only. In this case, the PTMC would not be used. A block diagram for a flexible, general-purpose network processor blade is shown below.

PMC-8500Q: SONET Quad OC-3 Interface PMC Module

ADLINK 6U PcompacPCI Network Processor Blade

The ADLNIK cPCI-6240 is an Intel® IXP2400 Network Processor-based PICMG 2.16 compliant Network Processor Board. Dual PMC sites are provided to support PTMC and control plane processing PMC modules. An on-board Ethernet switch provides flexibility in the routing of packets to and from the network processor, front panel, and PICMG 2.16 interface. The cPCI-6240, in conjunction with ADLINK Framer-Mapper Quad OC-3 or Single OC-12 PMC-8500 modules, provide an ideal solution for the conversion of SONET ATM, or Packet-over-Sonet (PoS) to IP (Gigabit Ethernet). The cPCI-6240 is designed to meet the needs of network access and edge applications for wireless and broadband markets including BSC/RNC/MSC, CMTS, DSLAM, FTTx, NG-DLC, etc. The cPCI-6240 delivers ultimate performance in multi-service switch and layer 4-7 applications including firewall, IDS, and load balancing, etc.

Features of cPCI-6240

The cPCI-6240 combines the Intel® IXP2400 network processor, Quad MAC and Mapper Framer silicon onto a highly integrated CompactPCI board. With this higher level of integration, users can reduce the board count and cost of future telecommunication platforms.

  • Intel® IXP2400 Network Processor
  • 6U CompactPCI supports 64-bit, 66MHz universal operation
  • PICMG 2.0, 2.1, 2.16, 2.9, 2.15 Compliant
  • Dual Front Panel 10/100/1000Mbps Ethernet Ports
  • Dual 10/100/1000Mbps Ethernet port on J3 per PICMG 2.16
  • Onboard Gigabit Ethernet Switch for maximum flexibility
  • One PTMC site provides 16-bit 50MHz Utopia Bus
  • One PrPMC/PMC site provides additional control plane processor
  • Serial Debug Port with Front or rear I/O access
  • Additional Dual Rear I/O GbE Ports for transition module
  • Optional dual optical GbE ports on the font panel
  • Boot monitor, Diagnostic utility and VxWorks BSP supported
Contact Information

ADLINK Technology Inc.
8900 Research Drive
Irvine, CA 92618
866.4.ADLINK Telephone
949.727.2099 Fax