Intel Unveils Plans for x86-based SoC

By Craig Szydlowski

Twenty years after the launch of the Intel386™ microprocessor, Intel is developing a new generation of x86-based system-on-a-chip (SoC) processors. The processors will be released in 2008. Preliminary details about "Tolapai," the first in what will be a family of enterprise-class SoC products, were disclosed at the Intel Developer Forum (IDF) in Beijing, China. Tolapai will include the new Intel® QuickAssist Integrated Accelerator, which increases the performance of specific functions like security encryption.

Tolapai integrates a processor core, memory controller, I/O, and specific function processing into a single chip. Although Intel hasn't publicly disclosed the Tolapai feature set, reliable speculation suggests that the design is based on the Intel® Pentium® M processor core. That core is clocked at 600 MHz to 1.2 GHz. The target power-dissipation range is 13 to 25 W. Tolapai will be an embedded component with extended manufacturing life-cycle support.

This product is expected to catch the eyes of embedded developers, who must strike a balance between space constraints, input-output functions, and performance. Its small footprint and low power consumption will benefit small-form-factor designs, such as Com Express and PC/104. Today, those designs widely use the Intel Pentium M processor. By putting the processor, Northbridge, and Southbridge into a single package, Intel hopes to reduce design complexity and its customers' time to market.

With Intel's already strong presence in security appliances and converged Private Branch Exchanges (PBXs), Tolapai may be able to reach down to lower-end systems. Because this segment is very cost sensitive, developers are always looking for higher integration and lower power. In traditional embedded systems, such as industrial automation and test and measurement, one should expect that Intel will offer Tolapai with a diverse mix of I/O. This aspect also can help to reduce BOM cost.

The integrated memory controller is expected to support DDR2 with speeds ranging between 400 and 800 MHz. Among other I/O, Tolapai is conjectured to contain Gigabit Ethernet, Time Division Multiplexing Bus (TDM), UARTs, a 16-bit PCI bus, PCI Express®, USB 2.0 ports, Serial ATA ports, Controller Area Network (CAN), and a large number of general-purpose I/O.

Intel QuickAssist Integrated Accelerator should set Intel's SoC apart from rival offerings. The integrated accelerators perform application-specific processing, such as security and telephony. In doing so, they free up CPU cycles for higher-level application processing. Some of the enhanced security services, which run at Gigabit line rates, may include AES, 3DES, RC4, MD5, and SHA-XXX. Integrated accelerators may work in conjunction with the TDM and Ethernet peripherals to enable converged telephony applications.

These enhanced services will be supported through a software layer (accelerator-abstraction layer), which allows applications to easily manage accelerators and protect software investment. An application programming interface (API) provides software abstraction using a driver model. As a result, applications can call services without getting involved with implementation details. As future SoC products are released, they'll support the same API and maintain backward binary compatibility.

Today, many embedded systems connect to a network and need to protect themselves from security breaches. The Intel QuickAssist Integrated Accelerator will add value by providing security functionality with minimal impact to the rest of the system. Developers can decouple security processing from time-critical applications and see performance gains that can't be measured in clock speed alone. Tolapai is further evidence that Intel is looking beyond Megahertz to deliver solutions that address the performance, integration, and power requirements of embedded developers.


Craig Szydlowski is a contributing editor to Embedded Intel® Solutions. He is a technology writer with over twenty years of semiconductor and embedded market experience working for Intel, IBM and Siemens. He holds a BSEE from Yale University and a MBA from the Wharton School.