Virtual Approach Leads to Power Optimization for Real-Time Systems

By Graham Hellestrand

Designers of most electronic systems are concerned with minimizing the amount of power that systems consume. This is particularly true in the case of battery-powered portable (often wireless) consumer electronics systems such personal digital assistants (PDAs) and cell phones. Consumers are becoming increasingly aware of product aspects such as battery life, which often outweighs increased functionality as a key feature effecting purchase decisions.

Products that consume less power have a significant advantage in today’s extremely competitive markets. Each generation of product planning must satisfy substantial increases in functionality and performance plus substantial reductions in power consumption. In the past, the focus of next-generation product planning has been concentrated largely on the micro-architecture of the underlying microprocessing units. However, the improvement of the processor micro-architecture typically yields only second- or third-order effects with regard to improving performance. By comparison, the overall hardware (platform) architecture, and the architecture and algorithmic content of the software that runs on, it both have first-order effects at the system level.

Creating optimal low-power designs requires making sophisticated tradeoffs in the hardware architecture, the software architecture, and the underlying software algorithms. The creation of successful power-sensitive designs requires system architects and engineers (both hardware and software) to accurately and efficiently perform and quantify such tradeoffs. To achieve this, they require the ability to access and analyze power data early in the design process.

Virtual system prototypes (VSPs) can be used to model, analyze, and optimize real-time systems in the context of power. Small changes in the hardware architecture and software algorithms of electronic designs can significantly affect the power consumption of a system.

Characteristics such as performance and power for a complex system such as a cell phone—including its software—cannot be represented and computed as a formal mathematical problem. The only realistic solution for determining such characteristics is some form of simulation.

One option for this simulation is hardware acceleration and/or emulation. Though improvements have been made in the co-development of software and hardware systems, acceleration-emulation can not typically commence until well into the design cycle when the hardware portion of the design is largely complete. At this late date, the design team’s ability is limited with regard to exploring, evaluating and optimizing the hardware architecture. In addition, FPGA implementations of processors typically are slow, executing software at around 1 MIP—about 50 times slower than a virtual processor model of the same processor.

The related concepts of virtual prototypes (VPs) and virtual system prototypes (VSPs) provide a solution. A VP is a functionality-accurate and timing-accurate software model of the hardware portions of an electronic system, typically including processor cores, memory subsystems, peripherals, buses, bridges, mechanical and RF devices, etc. By comparison, a VSP is a model of the entire system—both the VP and the software that will run on it.

A key advantage of using a VSP is that the hardware and software portions of the system can be developed and evaluated concurrently. A VSP allows different hardware architectures to be quickly and easily tested and analyzed under real software workloads. While hard real-time software code is being developed, its execution yields trace data (from probes inserted into the models) from which performance (timing, reaction times, latency times, etc.) and power data alongside normal debug data.

Optimizing the hardware and software components of systems with complex objective functions is non-intuitive. Sophisticated tradeoffs between the hardware architecture and the software and algorithmic loads that are run on the hardware cannot be achieved by intuition or by formal mathematical analysis alone.

The solution is to use a high-performance, functionality-accurate VSP that allows objective functions such as power consumption to be determined in the context of alternative hardware and software architectures running real software workloads.



Graham Hellestrand is chairman and chief of technology strategy for VaST Systems Technology. He is also emeritus professor of computer science at the University of New South Wales, Australia. Hellestrand holds B.Sc. and Ph.D. degrees in computer science and engineering, and an MBA. He is a Fellow of IEEE and Institution of Engineers (Australia). He can be reached at g.hellestrand@vastsystems.com.