Repurpose to Address the Challenges of Developing High- Performance SoCs

By Sam Sanyal, MosChip Semiconductor

For developers, a key goal is to integrate high-performance and higher-bandwidth functional connectivity blocks upon a system-on-a-chip (SoC). While addressing the core need of a specific vertical, additional functionality also may be added. It could be to address legacy or next-generation requirements or simply to have an extra edge over the competition. For connectivity, there’s a growing need to address this trend. For example, how can one best support Universal Serial Bus (USB) 2.0 once going after next-generation USB 3.0 in a single solution? What about adding other value-added features on top of this?

To do this upon an SoC, embedded designers should consider creating a baseline SoC with multiple functional blocks. From there, repurposing can be quickly achieved. Multiple vertical- specific SoCs can be repurposed from such a baseline with incremental design changes possible—for example, to provide USB 2.0 and 3.0 applications. With a baseline, geometry reduction shouldn’t be an issue. When repurposing, reduced geometry will be important along with noise margin, voltage, heat generation, signal integrity from simultaneous switching noise (SSN), etc.—to name a few. Power consumption for repurposed solutions will of course factor in as well. Every functional block on the chip has its own power-consumption requirements, which differ depending on the focus of functional blocks. At the system level, this also will add complexity to the power distribution network (PDN).

The above approach is highly applicable to multi-connectivity peripheral platforms. Designers can address USB 2.0, 3.0, etc. on a single die while still having the potential to repurpose in the future. In other words, one could have multiple connectivity blocks and configure them through two different modes: hardwired (factory configured) or EEPROM or, alternatively, Flash programmable (user choice). This choice will add design flexibility to the overall system. The concept of a baseline SoC built for high-performance repurposing is a good approach for the embedded community, as it allows a more simplified, cost-effective method to build a family of products to suit various needs.

While there are clear advantages to repurposing, there also are some disadvantages in the short term. These disadvantages can be offset by designing a proper board layout and power-distribution network (PDN) and using good optimization design tools. It may not be cost effective or meet a short turnaround time. In the long haul, however, this approach will help designers more quickly address multiple appropriate vertical applications. A baseline approach significantly addresses cost sensitivity while providing quicker design turnaround times as market application needs change.

The driving forces behind this strategy are cost sensitivity and quick turnaround times for “got-to-have-it-now” consumer verticals. Two key verticals are pushing the need for higher bandwidth and performance-oriented SoC: storage and multimedia/ image processing. The envelope also is being pushed by additional technological requirements like security, content protection, and display or transfer of content. As such, it’s crucial for highly integrated system platforms to ensure zero interference in performance and low power consumption. These are true challenges for the embedded community.

With high-speed connectivity, the newly introduced Super- Speed USB 3.0—transferring data at 5 Gbps—is a new addition to the high-speed IO block. It will definitely address the need for transferring or streaming larger data files with significant power and performance enhancements (at a 10X faster rate than USB 2.0). But designers will be challenged in integrating USB 3.0. The key will be an optimized ratio of density and functions to meet the critical power criteria of system designers and competitive performance criteria. Of course, there also are concerns for cost and time to market.

Spinning a die as a whole functional block may have shortterm design advantages. However, a die with multiple functional blocks best addresses changing dynamics like power consumption. Embedded design engineers face obstacles like a shorter design cycle, increased performance targets, reduced costs, diverse applications, and more. It’s more important than ever to be able to quickly repurpose a die and win the race to market while ensuring high performance. Just be sure to start with a solid baseline design.

Sam Sanyal is the senior technical marketing manager at MosChip Semiconductor. He has nearly 26 years of experience in the semiconductor industry in various applications, design, FAE, and technical marketing management positions. Sanyal has published and presented a number of papers in various magazines and forums. He holds an MSECE from Cal Poly University, a BSEE from Texas A&M, and a BSc in physics from Calcutta University in India. Sanyal can be reached at sam@moschip.com.