Power Trumps Time-to-Market as Main Driver

By John Blyler

Learning about low power design takes a lot of energy. Over the last several months, I’ve interviewed chip and board companies, IP vendors, EDA suppliers, power organizations, standard bodies and even software development firms.

Each of these groups has a different perspective on the low power problem. Their solutions attest to the range and variety of these perceptions. Yet they also share a common understanding about the changing landscape for electronic products, namely, that power efficiency is now a critical part of the power budget. Let me explain.

In the past, architects would divide up available power – say, battery capacity for a given usage rate – and then allocate a portion of that total power (minus a small reserve) to each block in the chip or board design.

However, today’s power budgets come with an additional caveat: each block is expected to provide a power efficiency improvement as a way to reduce previous power levels. This mandate for efficiency is needed to offset the diverging rise in feature sets with a lack of improvement in battery technology. (See “Chip Designers Scramble For Low Power Solutions,” in the April 15th Low Power Design e-letter.)

This insistence on power efficiency has forced chip block designers to accelerate their collaboration with both board-level designers and software developers (device drivers, RTOS, OS and applications). In turn, board-level developers have accelerated their movement toward power saving smaller form factor (SFF) boards and lower power interface designs.

In the past, Time-to-Market (TTM) considerations have been the big driver for system-level awareness. TTM goals have been the main reason for collaboration between hardware chip-package-board and software design teams. But this has changed. While TTM is still important, power efficiency has eclipsed it as the more critical design driver.